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Upzoning the Semiconductor

How America can lead in innovation without exporting productivity 

Picture a city. The population is doubling every two years. Developers are running out of square footage within the city limits to house the growing population. The solution is clear: instead of building out, they’ll start building up. Where there once were single family homes, there will now be apartment buildings, condos, multiplexes, brownstones, housing dozens where there once were only a few.

Much like our beleaguered, overstuffed city, the answer to semiconductor innovation lies in how one can optimize the square footage and introduce a density of capabilities that provide the necessary operational and performance capacity for modern devices. Instead of attempting to squeeze as many IP blocks as possible onto each microchip, we can encourage a strategically enhanced shift in design and manufacturing to prioritize components produced at optimized nodes that function as a whole. Just as an expanding city may rely on a new skyscraper in one neighborhood and opt for multi-family dwellings in another, a next generation mobile communications system may rely on a component produced at an advanced node to handle its compute requirements and opt for a component produced at a mature node to operate its RF transceiver. Now it is time to ask: how best can a series of system components (chiplets) produced at both advanced and mature process nodes, be packaged together to take advantage of all technology capabilities in the toolbox, while simultaneously serving the needs of each individual customer?   

The answer: heterogenous integration. 

Running out of chip real estate 

For the past several decades, companies have advanced technology and engineering breakthroughs to keep Moore’s Law alive, pushing process nodes down to nanometers in the low single digits. Despite the shrinking of these transistors, the chips themselves will continue to get bigger as designers and manufacturers work to incorporate as much functionality and performance as possible in the space allotted. Also factored into this innovation trap is that larger chips typically mean lower manufacturing yields, resulting in higher costs. Another path is necessary. 

With heterogeneous integration in the development toolbox, manufacturers can incorporate components and chips fabricated at their optimal process nodes and otherwise incompatible materials for a specific functionality, bringing them together to create a higher functioning system. Instead of continuing to scale the individual nodes, this approach proposes integrating systems where each component is optimized for the intended application, facilitating the creation of a more effective chiplet without worrying about bottlenecking functionality. Refining capability through effective distribution of square footage upstream will lead to enhanced productivity through optimized packaging downstream.  

Innovation through collaboration 

The U.S. is an internationally recognized leader in semiconductor R&D, but when it comes to manufacturing, we face a lengthy path towards true global leadership. America is home to numerous manufacturing facilities, spread across the country – often in concert with other companies, universities, and research organizations. Rather than expect each of these facilities to produce an advanced, single digit nanometer, leading edge chip, we can instead unite the currently disconnected facilities from across the nation to produce chips that can be packaged together to create an advanced fully integrated system.   

This collaboration, a kind that is a hallmark of American innovation, frees up innovators to focus on optimized design and manufacturing for a specific component given its intended functionality rather than sacrifice area or yield to accommodate disparate technologies on a single chip. This approach gifts designers and manufacturers the freedom to innovate at a smaller level, fine-tuning their piece of a high performing puzzle. 

Designing the future 

The CHIPS Act has dramatically changed the outlook for the domestic semiconductor industry. Acknowledging a need for rapid growth to remain competitive, the U.S. government passed the most comprehensive semiconductor-focused bill in history. This once-in-a-generation investment in the semiconductor industry includes three key provisions to guide the resurgence of this industry: direct funding and tax credits to incentivize domestic production, DoD’s Microelectronics Commons to specifically focus on technologies critical to ensure our national security, and research & development funding to strengthen the domestic ecosystem. This R&D funding will support the establishment of the National Semiconductor Technology Center (NSTC), the National Advanced Packaging Manufacturing Program (NAPMP), up to three new Manufacturing U.S.A. Institutes, and funding for a NIST metrology center. 

This legislation targets a major issue: how to turn American innovation into American growth. America is filled with brilliant designers and technologists, yet our record number of patents is not translating to domestic fabrication of their innovations. Giving organizations a tax incentive to build and produce in America pushes us towards a path to continue to lead in innovation without exporting productivity. These incentives chart a course for the creation of an entire, widely accessible system.  

Heterogeneous integration of chiplets coupled with design libraries that are available to all will usher in a new future for accessible design innovation. Start-ups and universities with access to these tools will be able to experiment and create new system solutions in ways that they weren’t previously capable of. Freeing up innovation for the greater population through heterogeneous integration has the potential to spur an increase in domestic production of high quality optimized chiplets that could provide an extra layer of protection for national security and be a boon to the economy.  

Realizing our potential 

America has a fresh opportunity to upzone the semiconductor by reinvigorating advanced packaging technologies within the domestic ecosystem. Through the funding and incentives allocated through the CHIPS Act, new innovations in circuit and systems design, thermal management, and advanced materials and substrates – all critical to heterogeneous integration – can be accelerated.  

A renewed focus on this critical industry presents a unique opportunity to drive innovation with intention, focusing on the elements of American industry that show the most promise for growth and global leadership. Heterogeneous integration will free up fabs to refine their current processes, knowing that eventually their work will become part of an advanced fully optimized and integrated system. 

We’re running out of chip real estate, but a lateral limitation just means there’s room for vertical innovation. The future of the semiconductor industry is an evolution from transistor scaling to system optimization. To realize this fully, we must encourage the NSTC and NAPMP to embrace heterogeneous integration. 

Jonathan Prange

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Jonathan Prange

Jonathan Prange is a Business Strategy Lead at MITRE Engenuity. In this role, he works closely with key industry stakeholders and members of MITRE Engenuity’s Semiconductor Alliance to help shape and communicate a strategy for planning and operationalizing the National Semiconductor Technology Center (NSTC) as part of the recently-passed CHIPS Act.  

Before joining MITRE Engenuity, Jonathan held a variety of roles at Dow, and later DuPont, from Senior Chemist to Global R&D Manager. He was responsible for commercializing multiple products within both the Advanced Packaging and Emerging Technologies business units. 

Jonathan received his B.S. in chemistry from Purdue University followed by a Ph.D. in chemistry from Stanford University.